We just witnessed a significant semiconductor industry related non-cash trade deal take place on Twitter/X.
U.S. Commerce Secretary Lutnick expresses concerns in a conversation with ASML executives that China has an EUV lithography system as ASML denies shipping such scanners to the PRC.
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Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer.
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This roadmap provides an in-depth analysis of Intel’s current plans for its chip production capacity.
The NYT recently said it’s almost impossible to build robots without China. There are counter-examples very close to home, however …
Intel’s enhanced 18A-P has entered risk production, laying the groundwork to ramp the node into full production in the coming months.
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SemiAnalysis has published the first teardown from its new in-house lab, focusing on the minimum local metal pitch on SMIC’s third-gen 7nm at 32.5nm.
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TSMC is exploring panel-level packaging and is working on its CoPoS technology, but the company’s Kevin Zhang says wafer-level packaging technologies is considerably more advanced than panel-level packaging.
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Fashion brands struggle to adopt new technologies despite constant innovation. PDS and Future Fashion Assembly aim to bridge the gap between solutions and implementation.
TSMC is executing the largest manufacturing expansion in semiconductor industry history that combines simultaneous multi-fab N2 ramps, AI-driven manufacturing optimizations, and massive CoWoS/SoIC packaging capacity expans…